1. Field of the Invention
The present invention relates to a deep trench capacitor of a dynamic random access memory (DRAM) cell and, more particularly, to a method of forming a capacitor dielectric structure to increase the capacitance of the deep trench capacitor.
2. Description of the Related Art
There is much interest in reducing the size of individual semiconductor devices in order to increase their density on an integrated circuit (IC) chip, thereby reducing size and power consumption of the chip, and allowing faster operation. In order to achieve a memory cell with a minimum size, the gate length in a conventional transistor must be reduced to decrease the lateral dimension of the memory cell. However, the shorter gate length will result in higher leakage currents that cannot be tolerated, and the voltage on the bit line must therefore also be scaled down. This reduces the charges stored on a storage capacitor, and thus requires a larger capacitance to ensure that stored charges are sensed correctly. Recently, in fabricating highly-integrated memory devices, such as dynamic random access memory (DRAM), a deep trench capacitor has been developed within a silicon substrate without consuming any additional wafer area.
In order to prolong the data retention time, the capacitance of the storage capacitor must be increased by either increasing the capacitor area, decreasing the effective dielectric thickness between the capacitor plates, or increasing the dielectric constant (k) of the capacitor dielectric. However, increasing the capacitor area conflicts with the need to shrink the memory cell, and reducing the dielectric thickness is difficult because the dielectric thickness has already been reduced to a practical minimum. Therefore, improving the capacitor dielectric with a high dielectric constant is a way to provide adequate capacitance in view of shrinking cell size. In a conventional method, a multi-layered oxide/nitride/oxide structure, serving as an ONO structure, is employed as the capacitor dielectric. Because the dielectric constant of the silicon nitride (k=7.6) is 1.5xcx9c2 times larger than that of the silicon oxide (k=3.9), the nitride layer in the ONO structure can increase the capacitance of the deep trench capacitor. The oxide layer in the ONO structure is employed to repair the damaged interface. Nevertheless, the critical thickness of the ONO structure has a limitation of 5xcx9c10 nm, the dielectric constant of the ONO structure only reaches approximately 7, and problems of difficult process, low yield, high process cost, and leakage current occur.
Recently, a stacked nitride/oxide layer, serving as a NO structure, has been employed to form the capacitor dielectric. FIG. 1 is a sectional diagram showing a conventional deep trench capacitor. A DRAM cell comprises a transistor 22 and a deep trench capacitor 20 having a bottom electrode plate 14, a capacitor dielectric layer 16 and an upper electrode plate 18. The bottom electrode plate 14 can be formed from the n+-doped region in a silicon substrate 10 surrounding a deep trench 12 or from a doped-polysilicon layer that conformally covers the sidewall and the bottom of the deep trench 12. The capacitor dielectric layer 16, a NO structure, comprises a SiN liner deposited on the sidewall and bottom of the deep trench 12 by low pressure vapor deposition (LPCVD) and thin oxide layer grown on the SiN liner by re-oxidation process. The upper electrode plate 18 is formed by filling the deep trench 12 with a conductive layer.
In the NO structure, the SiN liner with a dielectric constant 1.5xcx9c2 times larger than the dielectric constant of the oxide layer has a thickness of 40xcx9c80 xc3x85 and combines with the oxide layer of 3 nm thickness, thus the capacitance of the deep trench capacitor 20 is effectively increased. However, there is still a problem of leakage current caused by the SiN liner. Also, during deposition of the SiN liner, the process gases, such as SiH4 and NH3, cause pinhole structure defects in the SiN liner. Although the oxide layer grown on the SiN liner can repair the defects, decrease the pinhole density and reduce leakage current to achieve a preferred distribution of breakdown voltage, the SiN liner is too thin to increase the dielectric constant of the NO structure. Thus, a method of increasing the dielectric constant of the capacitor dielectric layer 16 without exceeding the thickness limitation, thereby solving the aforementioned problems, is called for.
The present invention provides a method of forming a capacitor dielectric structure that is a NO structure with a nitride layer to increase the dielectric constant and ensure the electrical reliability of the capacitor dielectric structure.
The method of forming capacitor dielectric structure comprises steps of providing a semiconductor substrate having at least a predetermined capacitor structure, using silicon nitride deposition to form a SiN layer on the predetermined capacitor structure, using a reoxidation process to grow an oxide layer on the SiN layer, and using a nitridation process with N2O as a reactive gas to form a nitridation layer on the oxide layer.
Accordingly, it is a principle object of the invention to provide a method of forming a capacitor dielectric structure that may be applied to the formation of a deep trench capacitor or a stacked capacitor in DRAM.
It is another object of the invention to provide a nitridation layer on a NO structure to increase the dielectric constant of the capacitor dielectric structure.
Yet another object of the invention is to provide a nitridation layer on a NO structure to ensure the electrical property of the capacitor dielectric structure.
It is a further object of the invention to provide the capacitor dielectric structure to increase capacitance of a deep trench capacitor.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.